Data delay circuit and clock extraction circuit using the same

Details Data delay circuit and clock extraction circuit using the same Data delay circuit and clock extraction circuit using the same

H - Electricity

03

K

328/92

H03K 5/14 (2006.01) H03K 5/13 (2006.01) H03K 5/00 (2006.01)

Patent

CA 2006974

ABSTRACT OF THE DISCLOSURE A data delay circuit includes a first transistor, and a second transistor having a base, an emitter and a collector. Input data is applied to the bases of the first and second transistors. A constant-current source is coupled between the emitters of the first and second transistors and a negative power source. A capacitor is connected between the collector of the first transistor and the collector of the second transistor. The data delay circuit further includes a third transistor and a fourth transistor. The emitters of the third and fourth transistors ar connected to the collectors of the first and second transistors, respectively. The bases of the third and fourth transistors are provided with control data having a polarity opposite to that of the input data and having an adjusted amplitude level corresponding to a desired delay time to be given the input data. First and second load resistors are respectively coupled to the collectors of the third and fourth transistors through a positive power source. Delayed input data is drawn from the collectors of the third and fourth transistors.

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