Device for encoding/decoding n-bit source words into...

H - Electricity – 03 – M

Patent

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H03M 5/14 (2006.01) G11B 20/14 (2006.01)

Patent

CA 2281936

A device is disclosed for encoding a stream of databits of a binary source signal (S) into a stream of databits of a binary channel signal (C), wherein the bitstream of the source signal is divided into n-bit source words (x1, x2), which device comprises converting means (CM) adapted to convert said source words into corresponding m-bit channel words (y1, y2, y3). The converting means (CM) are further adapted to convert n-bit source words into corresponding m-bit channel words, such that the conversion for each n-bit source word is parity preserving (table I) (Fig. 1). The relations hold that mn1, p1, and that p can vary. Preferably, m = n + 1. The device is adapted to convert the 8-bit bitsequence '00010001' in the source signal into the 12-bit bitsequence '100010010010' and to convert the 8-bit bitsequence '10010001' into the 12-bit bitsequence '000010010010', in order to limit the repeated minimum transition runlength in the channel signal. Also other 8-bit sequences require a specific encoding into 12-bit bitsequences in order to limit the k- constraint of the channel signal to 7. Further, a decoding device is disclosed for decoding the channel signal obtained by means of the encoding device.

Cette invention concerne un dispositif qui permet de coder un train de bits de données d'un signal source binaire (S) en un train de bits de données d'un signal canal binaire (C). Le train de données du signal source est divisé en mots source de n bits (x¿1?, x¿2?). Ce dispositif comprend des systèmes de conversion (CM) qui vont convertir les mots source en mots canal correspondants de m bits (y¿1?, y¿2?, y¿3?). Les systèmes de conversion (CM) permettent en outre de convertir des mots source de n bits en des mots canal correspondants de m bits de sorte que la conversion pour chaque mot source de n bit assure un maintien de la parité (tableau I)(Fig. 1). A cette fin, les relations suivantes doivent être respectées: m > n?1 et p?1, étant entendu que p peut varier et que, de préférence, m = n + 1. Ce dispositif va convertir la séquence binaire de 8 bits "00010001" du signal source en une séquence binaire de 12 bits "100010010010", et convertir la séquence binaire de 8 bits "10010001" en une séquence binaire de 12 bits "000010010010", ceci de manière à limiter la longueur de plage de transition minimale répétée dans le signal canal. Les autres séquences de 8 bits nécessitent en outre un codage spécifique pour obtenir des séquences de 12 bits, ceci afin de limiter la contrainte k du signal canal à 7. Cette invention concerne également un dispositif de décodage qui permet de décoder le signal canal obtenu à l'aide du dispositif de codage.

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