H - Electricity – 03 – M
Patent
H - Electricity
03
M
H03M 7/46 (2006.01) G11B 20/14 (2006.01) H03M 5/14 (2006.01)
Patent
CA 2276296
A device is disclosed for encoding a stream of databits of a binary source signal (S) into a stream of databits of a binary channel signal (C) satisfying a (d,k) constraint, wherein the bitstream of the source signal is divided into n-bit source words (x1, x2), which device comprises converting means (CM) adapted to convert said source words into corresponding m-bit channel words (y1, y2, y3). The converting means (CM) are further adapted to convert n-bit source words into corresponding m-bit channel words, such that the conversion for ech n-bit source word is parity preserving (table I). The relations hold that m n 1, p 1, and that p can vary. Preferably, m = n + 1. Further, a sync word generator (9) is available for generating a q-bit sync word also satisfying said (d,k) constraint, the said sync word starting with a '0' bit and ending with a '0' bit, the device further comprising merging means (19) for merging said sync word in said stream of databits of the binary channel signal, and that q is an integer value larger than k(Fig. 1). Further, a decoding device is disclosed for decoding the channel signal obtained by means of the encoding device.
Cette invention a trait à un dispositif permettant de coder un train de bits d'information d'un signal source binaire (S) en train de bits d'information d'un signal canal binaire (C) satisfaisant une contrainte (d, k), le train de bits du signal source étant divisé en mots source à n-bit (x¿1?, x¿2?). Ce dispositif comprend des organes de conversion (CM) conçus pour convertir les mots source en mots canal correspondants à m-bit (y¿1?, y¿2?, y¿3?). Ces organes de conversion (CM) sont conçus, de surcroît, pour convertir des mots source à n-bit en mots canal correspondants à m-bit, de sorte que la conversion de chaque mot source à n-bit préserve la parité (tableau 1). Les relations sont telles que m > n ? 1, p ? 1, et que p est susceptible de variations. De préférence, m = n + 1. Le dispositif comporte, en outre, un générateur de mot de synchronisation (9) produisant un mot de synchronisation à q-bit satisfaisant la contrainte susmentionnée (d, k), ce mot commençant et se terminant par "0" bit. Le dispositif comporte également des organes de fusion (19) servant à faire fusionner le mot de synchronisation dans le train de bits d'information du signal canal binaire. Il est également établi que q est un nombre entier d'une valeur supérieure à k. (Figure 1). L'invention concerne également un dispositif de décodage destiné au décodage du signal canal obtenu au moyen du dispositif de codage.
Kahlman Josephus Arnoldus Henricus Maria
Nakagawa Toshiyuki
Nakamura Kousuke
Narahara Tatsuya
Schouhamer Immink Kornelis/antonie
Fetherstonhaugh & Co.
Koninklijke Philips Electronics N.v.
Sony Corporation
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