Divider for carrying out high speed arithmetic operation

Details Divider for carrying out high speed arithmetic operation Divider for carrying out high speed arithmetic operation

G - Physics

06

F

354/167

G06F 7/52 (2006.01)

Patent

CA 2008026

ABSTRACT OF THE DISCLOSURE A divider for producing a quotient by dividing a dividend by a divisor has an A register for holding dividend data, and a B register for holding divisor data. An adder/subtracter or arithmetic unit produces either one of a sum and a difference between the dividend data and the divisor data held in the A register and the B register, respectively. A D flip-flop holds sign bit data which is included in result data representative of a result of operation as produced by the adder/subtracter. An inverting gate inverts the sign bit data. A register sequentially shifts, every time the inverted sign bit data is inputted, the inverted sign bit data from the least significant bit (LSB) position while holding the inverted sign bit data. A shifter arithmetically shifts the result data produced by the adder/subtracter one bit to the left while storing a (logical) ZERO in the LSB position, and feeds the resultant data to the A register. A loop counter controls the adder/subtracter, register and shifter such that iterative processing for division is repetitively executed.

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