Dual storage mode dram architecture

Details Dual storage mode dram architecture Dual storage mode dram architecture

G - Physics

11

C

G11C 11/401 (2006.01) G11C 11/4193 (2006.01)

Patent

CA 2342516

A dual mode memory architecture is disclosed in which an additional address or mode pin is used to rearrange the architecture to increase refresh time and achieve an improved Soft Error Rate. The DRAM is selectively operable in a single DRAM cell per bit mode or a dual DRAM cell per bit mode. In the dual DRAM cell per bit mode, the reference dummy cells are disabled and two wordlines are simultaneously activated to access one single transistor and storage capacitor memory cell connected to each bitline of a pair of complementary bitlines. Therefore, both memory cells form a single dual DRAM cell. By accessing both memory cells of a pair of complementary bitlines, complementary data can be written to the dual DRAM cell. Due to the complementary data storage of the dual cell, the refresh period can be increased to reduce refresh power consumption, and the cell is less susceptible to alpha particle disturbances.

Affiliated with

Also associated with

Rating

Dual storage mode dram architecture does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dual storage mode dram architecture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual storage mode dram architecture will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1353220