Efficient hardware processor sharing

Details Efficient hardware processor sharing Efficient hardware processor sharing

G - Physics

06

F

G06F 9/38 (2006.01) G06F 15/78 (2006.01)

Patent

CA 2348306

An efficient hardware architecture and processing method permit pipelined processing stages to be shared in processing samples from a plurality of independent input sequences that are grouped prior to application to the processing arrangement. A high degree of processing engine efficiency and/or reduced delay for accepting new input samples are achieved by applying the signal sequence, {Yj: j=0,1,2,...,MN 1}, obtained by interleaving M signal sequences {Xij: j=0,1,2,...,N-1}, i=1,2,...M}. Thus, processing of sample Yj can start as soon as processing of sample Yj-M is finished. Accordingly, effective pipeline stage delay, Dp, can be reduced by a factor of M (from D max to D max /M) and the number of required engines (or, equivalently, required time) can be reduced by the same factor M.

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