Fabrication of stacked mos devices

Details Fabrication of stacked mos devices Fabrication of stacked mos devices

H - Electricity

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356/128

H01L 27/04 (2006.01) H01L 21/268 (2006.01) H01L 21/822 (2006.01)

Patent

CA 1197628

FABRICATION OF STACKED MOS DEVICES Abstract of the Disclosure In a process for manufacturing vertically integrated MOS devices and circuits, gate oxide and a gate are formed on a semiconductor substrate such as a silicon substrate. A layer of polysilicon is then deposited over the wafer, the polysilicon contacting the substrate silicon through a window in the gate oxide. The substrate silicon and the polysilicon are then laser melted and cooled under conditions that encourage crystal seeding from the substrate into the polysilicon over the gate. Subsequently, ions are implanted into the silicon substrate and the polysilicon to form source and drain regions. By introducing the source and drain dopants after melt associated seeding of the polysilicon, the risk of dopant diffusion into the device channel regions is avoided. - 1 -

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