Fault tolerant memory system

Details Fault tolerant memory system Fault tolerant memory system

G - Physics

06

F

G06F 11/08 (2006.01) G06F 11/10 (2006.01) G06F 11/16 (2006.01) G06F 11/18 (2006.01) G06F 11/20 (2006.01) G11C 29/00 (2006.01) H03M 13/15 (2006.01) G06F 11/14 (2006.01) G06F 11/267 (2006.01)

Patent

CA 2144980

Memory system (100) provides redundancy with a small increase in memory. Data and ECC words provide a first level of error detection/correction. Redundant addressing signals provide fault tolerance during propagation of address signals. Additional fault tolerance is achieved utilizing redundant clocks (115). Data bits are divided into a plurality of modules having a bit size capable of being corrected by the ECC, allowing address and data hardware to fail and valid data be provided. Redundant DRAM control signals assure proper DRAM operation, including refresh. In one embodiment a continuous data scrub operation is performed, with data written to the memory device (101) with ECC words for error correction. Simultaneously, data and ECC code words are applied to a second ECC device (505) which creates an ECC code word which is campared with thc ECC code word written to the memory device (101) with the data word.

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