Fet input/output pad layout

Details Fet input/output pad layout Fet input/output pad layout

H - Electricity

01

L

H01L 29/772 (2006.01) H01L 23/50 (2006.01) H01L 29/417 (2006.01) H01L 29/423 (2006.01)

Patent

CA 2209620

An object of the present invention is to provide a power FET hard to generate oscillations dependent on the interval between adjacent pads. The present invention has a plurality of pads for first terminals, which are placed in one side on a chip at unequal intervals, and a plurality of pads for second terminals, which are placed in the other side on the chip. Thus, the power FET is hard to generate the oscillations dependent on the interval between the adjacent pads.

L'invention est une méthode utilisée pour amener un FET de puissance à produire des oscillations basées sur la distance entre tampons adjacents. La méthode de l'invention utilise une pluralité de tampons pour un premier groupe de bornes placées à distances inégales d'un côté d'une puce, et une pluralité de tampons pour un second groupe de bornes placées de l'autre côté de la puce. Le FET de puissance est donc amené à produire des oscillations basées sur la distance entre tampons adjacents.

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