H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/149
H01L 29/40 (2006.01) H01L 21/203 (2006.01) H01L 21/285 (2006.01) H01L 21/338 (2006.01) H01L 29/812 (2006.01)
Patent
CA 1139454
Sho-24 10. FLOATING GATE VERTICAL FET Abstract of the Disclosure A planar field effect transistor (FET) includes a plurality of spaced-apart, floating Schottky barrier, epitaxial metal gate electrodes which are embedded within a semiconductor body. A drain electrode and a gate control electrode are formed on one major surface of the body whereas a source electrode, typically grounded, is formed on an opposite major surface of the body. The FET channel extends vertically between the source and drain, and current flow therein is controlled by application of suitable gate voltage. Two modes of operation are possible: (1) the depletion regions of the control gates and the floating gates pinch off the channel so that with zero control gate voltage no current flows from source to drain; then, forward biasing the control gate opens the channel; and (2) the depletion regions of the control gates and the floating gates do not pinch off the channel, but reverse biasing the control gate produces pinch off. Specifically described is a GaAs FET in which the floating gate electrodes are Al epitaxial layers grown by molecular beam epitaxy.
354743
Kirby Eades Gale Baker
Western Electric Company Incorporated
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