Graphics co-processor

Details Graphics co-processor Graphics co-processor

H - Electricity

04

N

H04N 1/405 (2006.01) G06T 17/00 (2006.01) G06F 15/72 (1990.01)

Patent

CA 2091034

ABSTRACT The present invention provides an apparatus and method for rendering graphic images as bit maps. The system includes an input for receiving digital input commands, a command interpreter to interpret the input commands and convert them into commands suitable for use inside the system, and several inputand output buffers. A halftone screening section and a rendering section output data suitable for use by a raster display or marking engine. The system can render multiple output pixels during each machine iteration, typically four pixels per clock cycle. The system can also apply halftone screens or gray fills to an image, rendering multiple pixels per clock cycle. A preferred embodiment is a single- chip graphics co-processor (GCP). - 40 -

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