High density v-mos memory array

Details High density v-mos memory array High density v-mos memory array

H - Electricity

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H01L 21/308 (2006.01) G11C 11/34 (2006.01) H01L 21/306 (2006.01) H01L 21/768 (2006.01) H01L 21/8242 (2006.01) H01L 27/108 (2006.01)

Patent

CA 1169557

ABSTRACT HIGH DENSITY V-MOS MEMORY ARRAY A method for providing high density dynamic memory cells which provides self-alignment of both V-MOSFET device elements and their interconnections through the use of a device-defining masking layer having a plurality of parallel thick and thin regions. Holes are etched in portions of the thin region with the use of an etch mask defining a plurality of parallel regions aligned perpendicular to the regions in the masking layer. V-MOSFET devices having self- aligned gate electrodes are formed in the holes and device interconnecting lines are formed under the remaining portions of the thin regions. A com- bination of anisotropic etching and directionally dependent etching, such as reaction ion etching, may be used to extend the depth of V-grooves. A method of eliminating the overhang of a masking layer after anisotropic etching includes the oxidation of the V-groove followed by etching to remove both the grown oxide and the overhang is also disclosed. BU-9-78-014

378812

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