High speed cmos differential interface circuits

Details High speed cmos differential interface circuits High speed cmos differential interface circuits

H - Electricity

03

K

328/185

H03K 17/687 (2006.01) G05F 3/24 (2006.01) H03K 19/0185 (2006.01)

Patent

CA 2022317

ABSTRACT:- High Speed CMOS Differential Interface Circuits High speed CMOS differential input and output interface circuits comprise input and output means arranged to be controlled by biasing means. The biasing means generates a bias voltage. The output interface has a single ended to differential translator as the input means and an differential output stage as the output means. The input interface has a input amplifier and detector as the input means, and a differential to single ended level translator as the output means. The input and output interfaces operate at 300MHz and 200MHz respectively using clock encoded data, and both are capable of interfacing with bipolar devices. A combined input/output interface operates at 200MHz using clock encoded data or 60MHz under normal clocked operation.

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