High speed packet resequencing system

Details High speed packet resequencing system High speed packet resequencing system

H - Electricity

04

Q

344/24

H04Q 3/00 (2006.01)

Patent

CA 2011714

HIGH SPEED PACKET RESEQUENCING SYSTEM Abstract of the Disclosure There is provided a resequencing process capable of sorting out-of-sequence cells as they transit through a high speed switching network, while maintaining a desired level of performance. The process comprises the steps of adding a time stamp to an incoming cell, prior to entering the switching network, wherein the time stamp corresponds to the current system time. Cells leaving the switching network are forwarded to a series of cell storage buffers as they exit the switching network. The status of each cell storage buffer is monitored such that an incoming cell can be directed to an empty buffer. The cell delay time of the buffer can then be set by comparing the difference between the cell time stamp and the current system time to the amount of time the incoming cell must be delayed before reaching an age maturity of k. Once the cell has reached maturity, they are allowed to exit the storage buffer. - i -

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