Improved method for isolating sio2 layers from pzt, plzt and...

Details Improved method for isolating sio2 layers from pzt, plzt and... Improved method for isolating sio2 layers from pzt, plzt and...

H - Electricity

01

G

H01G 4/08 (2006.01) H01L 21/02 (2006.01) H01L 21/76 (2006.01) H01L 27/08 (2006.01)

Patent

CA 2129838

An improved method for constructing integrated circuit structures in which a buffer SiO2 layer (203) is used to separate various components comprising ferroelectric materials (208) or platinum (202) is disclosed. The invention prevents interactions between the SiO2 buffer layer (203) and the ferroelectric materials (208), The invention also prevents the cracking in the SiO2 which is commonly observed when the SiO2 layer (203) is deposited directly over a platinum region (202) on the surface of the circuit. The present invention utilizes a buffer layer of material which is substantially inert with respect to the ferroelectric material (208) and which is also an electrical insulator to separate the SiO2 layer (203) from the ferroelectric material (208) and/or the platinum regions (202).

L'invention concerne un procédé de construction de structures de circuit intégré qui consiste à utiliser une couche intermédiaire de SiO2 (203) pour séparer divers composants constitués de matériaux ferroélectriques (208) ou de platine (202). Ce procédé empêche les interactions entre la couche intermédiaire de SiO2 (203) et les matériaux ferroélectriques (208). Il empêche également la fissuration du SiO2, phénomène fréquemment observé lorsque la couche de SiO2 (203) est déposée directement sur une zone de platine (202) à la surface du circuit. Selon ladite invention, on utilise une couche intermédiaire en matière inerte par rapport au matériau ferroélectrique (208) qui fait également office d'isolant électrique et sépare la couche de SiO2 (203) du matériau ferroélectrique (208) et/ou des zones en platine (202).

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