Integrated semiconductor wafer processing system

Details Integrated semiconductor wafer processing system Integrated semiconductor wafer processing system

H - Electricity

01

L

H01L 21/306 (2006.01) H01L 21/00 (2006.01) H01L 21/3213 (2006.01)

Patent

CA 2220046

An improved apparatus (16, 18, 20, 22, 24, 25) and method which offers an integral pre-strip rinse operation between etching operation and stripping operation. The present invention is designed to allow a semiconductor wafer (A) to undergo sequential processing of dry etching, wet pre-strip rinsing, dry photoresist stripping, and wet final rinsing in a single system.

Un appareil amélioré (16, 18, 20, 22, 24, 25) permet d'effectuer en continu une opération de rinçage avant le dénudage, entre les opérations d'attaque au plasma et de dénudage. L'invention permet de faire subir successivement à une plaquette de semi-conducteur (A) les opérations d'attaque par voie sèche, de rinçage avant le dénudage, de dénudage du vernis photosensible et de rinçage humide final, en n'utilisant qu'un appareil.

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