Inter-processor communication protocol

Details Inter-processor communication protocol Inter-processor communication protocol

G - Physics

06

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340/81

G06F 15/16 (2006.01) G06F 9/46 (2006.01) G06F 13/374 (2006.01) G06F 13/42 (2006.01) H04L 12/56 (2006.01) H04L 29/00 (2006.01) G06F 11/14 (2006.01)

Patent

CA 1277382

Abstract: Processors of a multiprocessor system communicate across bus via a low-latency packet protocol featuring per-logical channel input queues and output queues, different per- processor priorities for sending data packets and data packet- acknowledging "quick" messages, and separate buffers for receiving data packets and "quick" messages, respectively. Transmitted data packets afflicted by error, receive buffer overflow, and input queue-full conditions are discarded by the receiving processor and are retransmitted by the sending processor.

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