Interpolator increasing the output word rate of a digital...

Details Interpolator increasing the output word rate of a digital... Interpolator increasing the output word rate of a digital...

H - Electricity

04

L

H04L 5/00 (2006.01) H03H 17/02 (2006.01) H03H 17/06 (2006.01) H04J 3/02 (2006.01)

Patent

CA 2051583

A multiplex interpolator handles 4 series of multibit input words ....., Si, Si+1, .... applied in parallel at 32 kHz after conversion through an input series to parallel converter (SIPO) and produces 4 series of multibit output words at 256 kHz with the help of a parallel adder/subtractor (ADD) operated in multiplex to compute successively for each of the 4 series of input words, the output words 8Si, 7Si+Si+1, ...., Si+7Si+1, 8Si+1, ...., each addition of Si+1-Si being also computed by the adder/subtractor in two steps, first by subtracting (c1) Si from the accumulated (IVC) value and second, by adding (d1) Si+1 to the newly accumulated value, the adder/subtractor being initialized after each pair of steps prior to processing data pertaining to another of the 4 input words in a cyclic manner.

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