Lithographic image size reduction

H - Electricity – 01 – L

Patent

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Details

356/147, 356/192

H01L 21/70 (2006.01) H01L 21/033 (2006.01) H01L 21/308 (2006.01)

Patent

CA 1250669

Abstract Disclosed is a process for reducing lithographic image size for integrated circuit manufacture. A mask of photosensitive material having an opening of a minimum size dictated by the limits of lithography is formed on a substrate. Reduction in the image size is achieved by establishing sidewalls to the interior vertical surfaces of the opening by depositing a conformal layer, followed by anisotropic etching. The dimension of the opening is reduced by the combined thickness of the two opposite insulator sidewalls. In a specific direct application of the disclosed process, a photomask/stencil having a pattern of openings of a minimum size smaller than possible by lithography, per se, is formed.

549183

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