Method and apparatus for minimizing semiconductor wafer...

Details Method and apparatus for minimizing semiconductor wafer... Method and apparatus for minimizing semiconductor wafer...

G - Physics

01

R

G01R 31/26 (2006.01) H01L 21/66 (2006.01) H01L 21/683 (2006.01)

Patent

CA 2340718

A method and apparatus for minimizing or eliminating arcing or dielectric breakdown across a wafer (26) during a semiconductor wafer processing step includes controlling the voltage across the wafer (26) so that arcing and/or dielectric breakdown does not occur. By using an electrostatic clamp (50) of the invention and by controlling the specific clamp voltage, the voltage across a wafer is kept below a threshold and thus, arcing and/or dielectric breakdown is reduced or eliminated.

L'invention concerne un procédé et un appareil permettant de réduire ou d'éliminer la formation d'étincelles et/ou un claquage diélectrique dans un galette (26) pendant une étape de traitement de galette de semi-conducteur. Ce procédé consiste à réguler la tension appliquée à la galette (26) de façon à empêcher la formation d'étincelles et/ou un claquage diélectrique. Au moyen d'une pince électrostatique (50) selon l'invention et en régulant la tension spécifique de ladite pince, la tension appliquée à la galette est maintenue en-dessous d'un seuil, ce qui permet de réduire ou d'éliminer la formation d'étincelles et/ou un claquage diélectrique.

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