G - Physics – 06 – F
Patent
G - Physics
06
F
G06F 15/16 (2006.01) G06F 9/38 (2006.01)
Patent
CA 2107306
ABSTRACT OF THE DISCLOSURE A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units for execution and placement of results thereof within specified general purpose registers. Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers are provided and each time an instruction is dispatched to an available execution unit, a particular one of the intermediate storage buffers is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register or a designated alternate general purpose register.
Kahle James Allan
Kau Chin-Cheng
Ogden Aubrey Deene
Poursepanj Ali Asghar
Tu Paul Kang-Guo
International Business Machines Corporation
Rosen Arnold
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