Method for improving step coverage of dielectrics in vlsi...

Details Method for improving step coverage of dielectrics in vlsi... Method for improving step coverage of dielectrics in vlsi...

H - Electricity

01

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356/132

H01L 23/52 (2006.01) H01L 21/3105 (2006.01) H01L 21/311 (2006.01) H01L 21/768 (2006.01)

Patent

CA 1213075

METHOD FOR IMPROVING STEP COVERAGE OF DIELECTRICS IN VLSI CIRCUITS Abstract of the Disclosure Particularly for use in multilevel metallization structures in which the underlying topography consists of fine and sharply contoured conductor lines produced by dry etching, conformal or near planar dielectric coatings are produced by depositing a dielectric layer to a thickness over the conductor of at least three times the conductor thickness. The dielectric is then anisotropically etched back to a thickness comparable with that of the underlying conductor. By this method a smooth dielectric top surface can be obtained without the requirement for multiple processing steps characterizing alternative planarizing techniques. - i -

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