Method of fabricating self-aligned mos devices and...

Details Method of fabricating self-aligned mos devices and... Method of fabricating self-aligned mos devices and...

H - Electricity

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356/128, 352/82.

H01L 21/76 (2006.01) G11C 11/34 (2006.01) H01L 21/28 (2006.01) H01L 21/336 (2006.01) H01L 21/339 (2006.01) H01L 21/8242 (2006.01)

Patent

CA 1183955

METHOD OF FABRICATING SELF-ALIGNED MOS DEVICES AND INDEPENDENTLY FORMED GATE DIELECTRICS AND INSULATING LAYERS ABSTRACT OF THE DISCLOSURE A method is described for fabricating MOS devices of the type found in very large scale integrated circuits. According to the method described herein, various gate oxides and insulating layers are fabricated independently of each other in order to independently tailor their thicknesses and thereby provide improved isolation between gate electrodes and interconnects, and independently controllable operating characteris- tics for multiple gate electrode structures. The fabrication of a dynamic RAM memory cell, an overlapping gate CCD device and a self-aligned MNOS transistor cell are described using the disclosed method.

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