Method of fabricating vlsi cmos devices

Details Method of fabricating vlsi cmos devices Method of fabricating vlsi cmos devices

H - Electricity

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H01L 21/82 (2006.01) H01L 21/8238 (2006.01) H01L 29/49 (2006.01) H01L 27/092 (2006.01)

Patent

CA 1218760

Abstract: The present invention relates to a method of fabricating a CMOS device of the type that comprises substantially complementary-threshold-voltage NMOS and PMOS transistors which include silicide-on-doped polysilicon gates. The method is comprised of the steps of forming a polysilicon layer on a substrate; introducing p-type dopants only into regions of the layer from which PMOS-transistor gates are to be formed; driving sub- stantially all of the dopants into lattice sites in the regions of the layer and subsequently forming a silicide precursor layer on the polysilicon layer.

476517

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