H - Electricity – 01 – G
Patent
H - Electricity
01
G
H01G 13/00 (2006.01) H01L 21/02 (2006.01) H01L 27/06 (2006.01)
Patent
CA 2272170
A method of forming capacitors in a semiconductor device, involves providing a first insulating layer, providing a first mask with an array of apertures over the insulating layer, and etching an array of holes in the first insulating layer through said apertures in said first mask. A first electrode layer extending into the holes is formed over the first insulating layer. A second dielectric layer extends into the holes on said first electrode layer. A second electrode layer extends into the holes on the dielectric layer. The capacitors are patterned with a second mask. The capacitors can be subsequently connected into the circuit in a sequence of processing steps that only involve the addition two extra masks beyond those conventionally employed in integrated circuit manufacture.
Blain Stephane
Ouellet Luc
Marks & Clerk
Mitel Corporation
Zarlink Semiconductor Inc.
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