Module for packaging semiconductor integrated circuit chips...

Details Module for packaging semiconductor integrated circuit chips... Module for packaging semiconductor integrated circuit chips...

H - Electricity

01

L

356/134

H01L 23/538 (2006.01) H01L 23/50 (2006.01)

Patent

CA 1277434

MODULE FOR PACKAGING SEMICONDUCTOR INTEGRATED CIRCUIT CHIPS ON A BASE SUBSTRATE ABSTRACT An integrated circuit chip packaging structure, preferably having a semiconductor base substrate, i.e., silicon or gallium arsenide, alternating insula- tion and conductive layers on the base structure, at least two conductive layers being patterned into thin film wiring (i.e., thin film copper of approximately 5 microns), semiconductor integrated circuit chips connected to the upper-most patterned conductive layer, and means to connect the packaging structure to the next level of packaging (i.e., board or card). The thin film wiring layers typically each have coplanar ground, power and signal lines, with at least one power or ground line existing between coplanar signal lines to minimize cross talk. To facilitate efficient power distribution, lines of specific power levels of the patterned planes are connected to lines of the same power level on other patterned planes to form three dimensional power planes. To reduce package capacitance and keep the RC constant low, a personalized reference plane is incorporated. The personalized plane has insulating regions extending at least partially through the plane at predetermined locations that coincide with long signal lines on the wiring layers. The combined package provides a packaging alternative that has excellent electrical performance (i.e., speed; low RC constant, efficient power distribution), high density and thermal expan- sion matching between the underlying semiconductor structure and semiconductor chips mounted on the package. A high yield process for manufacturing the package is also disclosed.

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