Multiprocessor communication using reduced addressing lines

Details Multiprocessor communication using reduced addressing lines Multiprocessor communication using reduced addressing lines

G - Physics

06

F

354/234, 354/67

G06F 13/14 (2006.01) G06F 9/46 (2006.01) G06F 12/02 (2006.01) G06F 12/08 (2006.01)

Patent

CA 2026771

ABSTRACT A method for communication between multiple processors using registers that are accessed by four register select lines which are translated from the original system address. The address translation is performed off of the main processor board to reduce loading effects on the local bus and reduces the pin count of processor board. A signal representing which of the processors is currently active is used as a pseudo address line for the purpose of the translation. The original addresses of the I/O registers may be either input/output or memory mapped.

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