Non-volatile counter

H - Electricity – 03 – K

Patent

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352/39

H03K 21/00 (2006.01) H03K 21/40 (2006.01)

Patent

CA 2019581

A counter includes an array of memory cells arranged in groups of memory cells, each group designating a counting decade. Each group of memory cells includes first and second word strings, each capable of storing a data word, and a fault flag, capable of indicating which word string contains the data word. Sensing means is coupled to the memory array for checking the status of the memory cells and for generating fault signals upon detection of a fault in a memory cell. Logic means is coupled to the memory cells and to the sensing means for selecting the first or second word string in response to a fault signal, wherein upon detection of a fault in a first word string, the data word is written into a second word string. A central shifting unit is coupled to the memory array for reading a data word stored in a word string into the shifting unit, incrementing the data word, and writing the incremented data word into its respective word string.

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