Normally-off, gate-controlled electrical circuit with low...

Details Normally-off, gate-controlled electrical circuit with low... Normally-off, gate-controlled electrical circuit with low...

H - Electricity

03

K

328/200

H03K 17/06 (2006.01) H03K 17/687 (2006.01)

Patent

CA 1205877

NORMALLY-OFF, GATE-CONTROLLED ELECTRICAL CIRCUIT WITH LOW ON-RESISTANCE ABSTRACT OF THE DISCLOSURE An electrical circuit includes a JFET serially connected to an IGFET, the gate of the IGFET constituting the gate for the circuit. Biasing structure, such as a resistor, is connected between the circuit gate and the gate of the JFET for forward-biasing the P-N junction of the JFET extant between its gate and channel regions. When this P-N junction is biased by more than about 0.6 volts for silicon JFET, the JFET gate region injects current carriers into the JFET channel region, whereby bipolar conduction occurs in the JFET channel region and low on-resistance for the circuit is achieved. In a preferred circuit the biasing structure comprises an IGFET, which advantageously results in the circuit gate having a high input impedance.

447756

Affiliated with

Also associated with

Rating

Normally-off, gate-controlled electrical circuit with low... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Normally-off, gate-controlled electrical circuit with low..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Normally-off, gate-controlled electrical circuit with low... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1308657