Output buffer

Details Output buffer Output buffer

H - Electricity

03

K

328/189

H03K 21/10 (2006.01) H03K 19/00 (2006.01) H03K 19/003 (2006.01) H03K 19/017 (2006.01) H03K 19/0185 (2006.01) H03K 19/094 (2006.01) H03K 19/0948 (2006.01)

Patent

CA 1275455

ABSTRACT OF THE DISCLOSURE A CMOS output buffer provides high drive current without sacrificing speed and with minimum output signal distortion due to internal chip ground bounce or output signal ringing. The output buffer includes a pull-up circuit and a pull-down circuit which distribute switching current spikes over time. The pull-up circuit includes a P-channel FET and an N channel FET connected in parallel between an output terminal and supply terminal VDD, with an inverter connected between the gates of the N-channel and P-channel FETs to provide the proper phase for the P-channel FET as well a delaying turn-on of the P-channel FET with respect to turn-on of the N-channel FET. The pull-down circuit includes a pair of N-channel FETs connected in parallel between the output terminal and ground, and a delay resistance connected between their gates so that turn-on of one of the N-channel FETs is delayed with respect to the other.

519345

Affiliated with

Also associated with

Rating

Output buffer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Output buffer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Output buffer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1181477