Paged memory controller

Details Paged memory controller Paged memory controller

G - Physics

06

F

354/230.86

G06F 13/00 (2006.01) G06F 1/14 (2006.01) G06F 12/02 (2006.01) G06F 12/08 (2006.01)

Patent

CA 2028085

IMPROVED PAGED MEMORY CONTROLLER Abstract of the Disclosure A computer system has a processor coupled to a cache controller, uses page mode memory devices and performs page hit detection on the processor local bus. Column address and data values are latched by a memory controller on memory write operations to allow early completion of the cycle so that the next cycle can partially overlap. This allows the use of economical memories and yet have zero wait state page hit operation.

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