Pager decoding system

Details Pager decoding system Pager decoding system

H - Electricity

04

B

325/72

H04B 1/16 (2006.01) H04Q 7/16 (2006.01)

Patent

CA 1230164

15 ABSTRACT: "Pager decoding system." A pager decoding system which is suitable for use with signal formats, such as POCSAG, in which code words are sent in batches, each batch containing a syn- chronisation code word and (n-1) address/message code words, n being the number of code words in a batch, each code word comprising m bits. The pager is able to detect or regain synchro- nisation code word when the carrier signal is lost due to fading. When synchronisation is lost input data received by the pager is combed through by switching-on the pager for a duration of m bits at intervals correspond to (n+1) code words. The data received is stored in a shift register having m stages and in which a synchronisation code word can be assembled within two batch periods. Once the synchronisation code word has been detected the pager can be switched to a normal data receiver mode. In another fade recovery mode the (m-1)th, mth, and (m+1)th bit positions every nth code word are searched to see if a preamble or synchronisation code word is present. If none is detected after a predetermined number of bat- ches has been searched then the pager assumes the loss of synchronisation mode described above.

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