Peripheral processor architecture

Details Peripheral processor architecture Peripheral processor architecture

G - Physics

06

F

354/230.8

G06F 3/023 (2006.01) G06F 3/02 (2006.01) G06F 9/34 (2006.01) G06F 15/02 (2006.01)

Patent

CA 1168370

CT9-80-006 ABSTRACT An improved peripheral processor architecture wherein the function controlling information of a program is separated from portions of the sequence of execution controlling information and each are stored in the form of tables. The function controlling in- formation takes the form of a table including a plural- ity of function specifying entries. The function execution sequence controlling information takes the form of a table of pointers. In this invention, function controlling entries, each having a plurality of fields for defining, modifying, and specifying the functions and related data to be executed, need not be repetitively duplicated throughout the program. Instead, the shorter pointers to the function table entries can be provided in the sequence table in the sequence in which the functions are to be executed. In a keyboard display controller application, further economy of storage is obtained by retaining a first level of function specifying information in the sequence table in the form of a bit identifying whether the function to be executed is a complex function, in which case the pointer identifies an entry in the function control statement table, or whether the function to be executed is merely the display of information on the display, in which case the pointer in the sequence table entry specifies an entry in a guidance table.

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