Planar isolation technique for integrated circuits

Details Planar isolation technique for integrated circuits Planar isolation technique for integrated circuits

H - Electricity

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356/151

H01L 29/06 (2006.01) H01L 21/465 (2006.01) H01L 21/762 (2006.01) H01L 21/763 (2006.01) H01L 23/58 (2006.01) H01L 23/66 (2006.01)

Patent

CA 2016449

Through the use of a specifically configured buried dielectric region, devices with strict design rules, e.g., design rules of 0.9 micrometers and less, are significantly improved. In particular, the recessed dielectric region, e.g., field oxide, separating device areas in an integrated circuit, either has a buried conducting shield surrounding the periphery of the oxide or has a configuration such that the upper surface of the dielectric is no more than 20 nm below the upper surface of the silicon forming the device active region. By insuring a suitable configuration, parasitic capacitance resulting in slower operation is considerably reduced while leakage currents are maintained at an acceptable level.

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