H - Electricity – 01 – L
Patent
H - Electricity
01
L
H01L 29/78 (2006.01) H01L 21/22 (2006.01) H01L 21/332 (2006.01) H01L 21/336 (2006.01) H01L 29/10 (2006.01) H01L 29/417 (2006.01) H01L 29/739 (2006.01)
Patent
CA 2199013
A reduced mask process for forming a MOS gated device such as a power MOSFET uses a first mask (33) to sequentially form a cell body (50) and a source region (51) within the cell body (50), and a second mask step to form, by a silicon etch, a central opening (80, 81) in the silicon surface at each cell and to subsequently undercut the oxide (60) surrounding the central opening (80, 81). A contact layer (84) then fills the openings (80, 81) of each cell to connect together the body (50) and source regions (51). Only one critical mask alignment step is used in the process.
Procédé à nombre de masques réduit pour former un dispositif à porte MOS tel qu'un transistor à effet de champ MOS. Ce procédé consiste à utiliser un premier masque (33) pour former séquentiellement un corps de cellule (50) et une région source (51) à l'intérieur de ce dernier (50), et un second masque pour former, par attaque du silicium, une ouverture centrale (80, 81) à la surface du silicium au niveau de chaque cellule, et à attaquer ensuite latéralement l'oxyde (60) entourant cette ouverture centrale (80, 81). Les ouvertures (80, 81) de chaque cellule sont remplies d'une couche de contact (84) de sorte que le corps (50) et les régions sources (51) soient connectés entre eux. Seule une phase d'alignement de masque critique est utilisée dans ce procédé.
International Rectifier Corporation
Mccarthy Tetrault Llp
LandOfFree
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