G - Physics – 11 – C
Patent
G - Physics
11
C
356/2, 352/82.1
G11C 29/00 (2006.01) G11C 8/06 (2006.01) G11C 8/12 (2006.01)
Patent
CA 1187176
PROGRAMMALBE ADDRESS BUFFER FOR PARTIAL PRODUCTS Abstract of the Disclosure A programmable address buffer for coupling external addresses to a desired pair of internal memory addresses includes A and B address inputs 11 and 12, a B address output 15 coupled to the B address input 12, a first inverter I30 coupled to the B address input and a B address output, a first switch S2 coupled to switchably connect one of the A and B address inputs 11 and 12 to a node, an A address output coupled to the first node, a second inverter I10 connected to the first node, a third inverter I20 con- nected between the second node and an A output 14, and a second switch S1 coupled to the second node to switchably connect one of the first node or the second inverter I10 to the second node. In another embodiment an electrical circuit for controlling the addressing of functional sections of a partially functional product includes a first pin 100 coupled by a first fuse F1 to a first address buffer 150, and a second pin 110 coupled by a second fuse F5 to a second address buffer 160, a fusible connection F4 between the second pin 110 and the first buffer 150, and fusible con nections F2, F3, F6, and F7 to each address buffer to con- nect that address buffer to either of two selected poten- tials corresponding to the desired state of that buffer.
423965
Fairchild Camera And Instrument Corporation
Smart & Biggar
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