H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/117, 356/135
H01L 23/02 (2006.01) H01L 23/495 (2006.01) H01L 23/58 (2006.01) H01L 23/60 (2006.01) H05K 1/02 (2006.01) H05K 3/34 (2006.01)
Patent
CA 1255812
ABSTRACT A semiconductor chip package configuration and a method are disclosed for facilitating testing of the chip package and mounting of the chip package on a substrate by forming one or more lead alignment bars in interconnecting relation with adjacent leads on the chip package, the lead alignment bars being formed from a material providing electrical isolation between leads during testing of the chip package and for providing physical spacing between the leads both during testing and later mounting of the chip package on the substrate so as to prevent adjacent leads from inadvertent contact. Preferably, the lead alignment bars are formed from a high resistivity material selected to provide sufficient conductivity between the interconnected leads for minimizing electrostatic discharge conditions therebetween, the material being sufficiently non-conductive to permit functional and dynamic testing of the leads. After testing of the chip package, it is mounted on the substrate with the interconnecting lead alignment bars then being removed to facilitate subsequent operation of the chip package.
514339
Fairchild Semiconductor Corporation
Smart & Biggar
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