Semiconductor device having narrow coplanar silicon electrodes

Details Semiconductor device having narrow coplanar silicon electrodes Semiconductor device having narrow coplanar silicon electrodes

H - Electricity

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356/134

H01L 21/84 (2006.01) H01L 21/033 (2006.01) H01L 21/339 (2006.01)

Patent

CA 1225464

14 ABSTRACT: A method of manufacturing a semiconductor device, for example an SPS memory having narrow coplanar silicon electrodes. The electrodes are formed by etching grooves or slots (10) having a width in the submicron range into a polycrystalline silicon layer (3), the slot width being defined by the oxidized edge (6) of a silicon auxiliary layer (5). The electrodes are alternately covered by silicon oxide and by a layer comprising silicon nitride. According to the invention, the electrodes formed covered by silicon oxide (3B, 13B) are first interconnected pair- wise, whereupon they are separated from each other in a separate etching step and are provided with self-aligned contact windows (15). Thus, the very narrow electrodes can be contacted without technological problems and memory cells of very small dimensions can be obtained.

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