Sidewall spacers for cmos circuit stress relief/isolation...

Details Sidewall spacers for cmos circuit stress relief/isolation... Sidewall spacers for cmos circuit stress relief/isolation...

H - Electricity

01

L

356/144

H01L 21/76 (2006.01) H01L 21/762 (2006.01) H01L 27/04 (2006.01)

Patent

CA 1245373

Abstract Sidewall Spacers For CMOS Circuit Stress Relief Isolation And Method For Making A method for forming fully recessed (planar) isolation regions on a semiconductor for the manufacture of CMOS integrated circuits, and the resulting semiconductor structure, comprising in a P doped silicon substrate with mesas formed therein, forming low viscosity sidewall spacers of borosilicate glass in contact with the sidewalls of those mesas designated to have N-channel devices formed therein; then filling the trenches in the substrate adjacent to the mesas with TEOS; and heating the structure until the boron in the sidewall spacers diffuses into the sidewalls of the designated mesas to form channel stops. These sidewall spacers reduce the occurrence of cracks in the TEOS by relieving internal mechanical stress therein and permit the formation of channel stops via diffusion, thereby permitting mesa walls to be substantially vertical.

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