H - Electricity – 04 – Q
Patent
H - Electricity
04
Q
344/25
H04Q 11/04 (2006.01) H04J 3/06 (2006.01) H04L 12/56 (2006.01)
Patent
CA 1224556
ABSTRACT The system switches data packets, with headers, from input junctions to output junctions. The series incoming packets are converted into parallel packets. The headers of cash incoming packet and the identity of the involved input junction are transferred to the address inputs of a control memory. The control memory supplies a new header which is assigned to the incoming packet, in replacement of the original header, in order to form the parallel outgoing packet with the remaining part of the incoming packet. A buffer memory is cyclically enabled for writing, in order to store the outgoing packets. Each parallel packet read out of the buffer memory is converted into a series packet which is assigned to the address multiplex. Queues store the addresses of a packet in the buffer memory, and are selectively enabled for writing, depending on information from the control memory. Each queue is assigned to an output junction. Responsive to a signal for indicating that one of the output junctions is enabled, the address contained in the corresponding queue is read, in order to find the output packet which is to be transferred to the outgoing junction in the buffer memory.
443673
Servel Michel
Thomas Alain
Servel Michel
Shapiro Cohen
Thomas Alain
LandOfFree
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