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Patent
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G01R 31/28 (2006.01) G01R 1/067 (2006.01) G01R 1/073 (2006.01)
Patent
CA 1290461
Abstract of the Disclosure Apparatus for testing the electrical integrity of printed circuit boards under test (BUTs), each BUT having a plurality of downwardly directed accessible nodes, the apparatus including support means for removably supporting the BUT, test circuitry including a plurality of upwardly directed channel nodes below the support means, connection means for electrically connecting the channel nodes to the BUT nodes, the connection means comprising a universal board carrying probes in a universal grid pattern, means to activate selective probes, and a translator board to make electrical connection between upper and lower conductors in different patterns.
564235
Smart & Biggar
Teradyne Inc.
LandOfFree
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