Universal semiconductor chip package

Details Universal semiconductor chip package Universal semiconductor chip package

H - Electricity

01

L

356/134

H01L 23/52 (2006.01) H01L 23/498 (2006.01) H01L 23/50 (2006.01) H01L 23/538 (2006.01)

Patent

CA 1315019

Abstract of Invention Disclosed is a semiconductor chip package comprising a plurality of programmable pads located on an exterior surface of the package, each pad being adapted for interconnection with a semiconductor chip. The package also includes a plurality of signal connec- tors located on an exterior surface of the package. In addition, the package includes a plurality of signal connections, each signal connection providing an electrically conductive path between an individual programmable pad and a corresponding individual signal connector. A plurality of dedicated power or ground connectors are also located on an exterior surface of the package. Conductive paths within the package provide apparatus for selectively connecting any programmable pad to a power or ground connector, any pad so connected also remaining connected to a cor- responding signal connector.

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