Vertically integrated cmos logic gate

Details Vertically integrated cmos logic gate Vertically integrated cmos logic gate

H - Electricity

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H01L 27/02 (2006.01) H01L 21/70 (2006.01) H01L 21/762 (2006.01) H01L 21/822 (2006.01) H01L 27/06 (2006.01) H01L 27/092 (2006.01)

Patent

CA 1206273

VERTICALLY INTEGRATED CMOS LOGIC GATE Abstract of the Disclosure A vertically integrated CMOS logic gate has spaced semiconductor layers with control gates located between the layers and insulated from them by gate oxide. Transistors formed in one semiconductor layer are vertically aligned with transistors formed in the other semiconductor layer. Pairs of vertically coincident transistors have common control gates and certain of the pairs have integral drain regions. Transistors in one layer are series connected in an open loop configuration and transistors in the other layer are parallel connected in a closed loop configuration. The logic gate function depends on voltages applied to the common control gates and to the open and closed loops. By the vertical integration, a two-input NAND or NOR gate can be made using less area than that required for two simple MOS transistors. -i-

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