Virtual wires for reconfigurable logic systems

Details Virtual wires for reconfigurable logic systems Virtual wires for reconfigurable logic systems

H - Electricity

03

K

H03K 19/00 (2006.01) G06F 17/50 (2006.01)

Patent

CA 2158149

A compilation technique overcomes device pin limitations using virtual wires. Virtual wires overcome pin limitations by intelligently multiplexing each physical wire among multiple logical wires and pipelining these connections at the maximum clocking frequency. Virtual wires increase usable bandwidth and relax the absolute limits imposed on gate utilization in logic emulation systems employing Field Programmable Gate Arrays (EPGAs). A "softwire" compiler utilizes static routing and relies on minimal hardware support. The technique can be applied to any topology and FPGA device.

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