Wafer level integration technique

Details Wafer level integration technique Wafer level integration technique

H - Electricity

01

L

356/133, 356/198

H01L 21/66 (2006.01) G01R 31/316 (2006.01) G11C 5/02 (2006.01) H01L 23/52 (2006.01) H01L 23/525 (2006.01)

Patent

CA 1236918

WAFER LEVEL INTEGRATION TECHNIQUE ABSTRACT OF THE DISCLOSURE Wafer level integration is provided by using individually integrated circuits on a wafer substrate and generating an electrically ordered matrix of func- tional integrated circuits assigned from a random dis- tribution of functional, partially functional, and non- functional circuits. Each circuit is individually tested for functionality and thereafter a conductive grid is formed on said wafer to interconnect all of the circuits on the wafer. Circuits that are tested as being non-functional are isolated prior to formation of the interconnecting grid by eliminating fuses that pro- vide connections between the defective circuit and the conductive grid. Each matrix row includes redundant decoder lines. The redundant decoder lines are pro- grammed to reassign functional circuits from a semicon- ductor wafer substrate location to a matrix row location in another matrix row having defective circuits. In this way, complete functional matrix rows are formed. Associated input and output lines are assigned in a similar manner to a correct bit position within an input and output byte.

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