Zero drain overlap and self-aligned contacts and contact...

Details Zero drain overlap and self-aligned contacts and contact... Zero drain overlap and self-aligned contacts and contact...

H - Electricity

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356/128, 352/82.

H01L 21/31 (2006.01) H01L 21/033 (2006.01) H01L 21/265 (2006.01) H01L 21/336 (2006.01) H01L 29/08 (2006.01) H01L 29/78 (2006.01)

Patent

CA 1197926

ZERO DRAIN OVERLAP AND SELF-ALIGNED CONTACTS AND CONTACT METHODS FOR MOS DEVICES ABSTRACT OF THE DISCLOSURE Fabrication techniques are described for the construction of MOS transistors to provide source/drain regions which are self-aligned and non-overlapping with respect to their gate electrode. The non-overlapping feature, along with other optimized device characteristics, are generally provided by defining a gate electrode over a substrate, forming an implant mask of dielectric, for example, on the sides of the gate electrode, and implant- ing a source/drain region such that the implant mask shields a portion of the substrate from implantation to provide a gap between a side edge of the gate electrode and the implanted regions. The source/drain region is then heat driven until its side edge is substantially aligned with the edge of the gate electrode. Self-aligned source/drain contacts are also provided using the implant mask to isolate the gate electrode from the contacts and inter- connects.

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