Data processing system common bus utilization detection logic

Details Data processing system common bus utilization detection logic Data processing system common bus utilization detection logic

G - Physics

06

F

354/234

G06F 9/46 (2006.01) G06F 11/34 (2006.01) G06F 11/36 (2006.01)

Patent

CA 1186415

ABSTRACT OF THE DISCLOSURE A common bus utilization detection logic that is used when a particular device connected to a common bus has been granted access to the common bus wherein bus access is granted on a priority basis. By positioning the bus utilization logic in priority positions on the common bus adjacent to the particular device whose bus use is to be detected, the bus utilization detection logic can determine when the common bus has been awarded to the particular device even though there may have been other devices simultaneously requesting access to the common bus. The bus utilization detection logic is used in a system analyzer connected to a data processing system having a common bus and permits the analyzer to be connected in the same manner as other devices are connected to the common bus. Also disclosed is a software analyzer and a data processing system having an asynchronous bus on which multiple words of data can b read from memory in response to a read request providing a starting memory address.

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