Method for controlling a vector register and a vector...

Details Method for controlling a vector register and a vector... Method for controlling a vector register and a vector...

G - Physics

06

F

354/230

G06F 15/80 (2006.01) G06F 9/30 (2006.01) G06F 15/78 (2006.01)

Patent

CA 1329656

ABSTRACT A multiprocessor sharing a vector register with several scalar units. To each of the addresses in each bank of the vector register belong memory modules for storing a vector element. The number of the memory modules belonging to an address is equal to the number of scalar units sharing the vector register. Each of the memory modules is identified by a new address number which is created by combining the address number and a number, known as the SU number, identifying each of the scalar units. The vector data relevant to each scalar unit are stored in memory modules having a SU number the same as that of the scalar unit. The data are stored inter- leaving all of the banks. When a scalar unit access is a vector data, it sends out the first address number and the vector length of the requested vector data. An address generator automatically generates new address numbers in succession, combining the address number and the SU number, and the data are accessed. When some of the scalar units are not used, the memory modules relevant to the unused scalar units are utilized for increasing the memory capacity of the active scalar units.

610997

Affiliated with

Also associated with

Rating

Method for controlling a vector register and a vector... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for controlling a vector register and a vector..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for controlling a vector register and a vector... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1312640