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Patent
G - Physics
06
F
G06F 9/40 (2006.01) G06F 9/00 (2006.01) G06F 9/30 (2006.01) G06F 9/32 (2006.01) G06F 9/355 (2006.01) G06F 9/38 (2006.01) G06F 9/44 (2006.01) G06F 15/80 (2006.01) G06F 17/50 (2006.01) F02B 75/02 (2006.01)
Patent
CA 2120232
Architectures and methods are provided for efficiently dividing a processing task into tasks for a programmable real time signal processor (SPROC) (10) and tasks for a decision-making microprocessor (2120). The SPROC is provided with a non-inter- rupt structure where data flow is through a multiported central memory. The SPROC is also programmed in an environment which requires nothing more than graphic entry of a block diagram of the user's design. In automatically implementing the block diagram into silicon, the SPROC programming/developing environment accounts for and provides software connection and in- terfaces with a host microprocessor (2120). The programming environment preferably includes: a high-level computer screen en- try system which permits choosing entry, parameterization, and connection of a plurality of functional blocks; a functional block cell library (2015) which provides source code representing the functional blocks; and a signal processor scheduler/compiler (2040) which uses the functional block cell library (2015) and the information entered into the high-level entry system to compile a program and to output source program code for a program memory and source data code for the data memory of the SPROC. as well as a symbol table which provides a memory map which maps SPROC addresses to variable names which the microproces- sor (2120) will refer to in separately compiling its program.
Krassowski Andrew J.
Montlick Terry F.
Robinson Jeffrey I.
Rouse Keith
R. William Wray & Associates
Star Semiconductor Corporation
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