H - Electricity – 01 – L
Patent
H - Electricity
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L
H01L 27/02 (2006.01) H01G 4/40 (2006.01) H01L 21/02 (2006.01) H01L 21/64 (2006.01) H01L 27/01 (2006.01) H01L 27/108 (2006.01) H01L 27/115 (2006.01)
Patent
CA 2106713
A method is provided for forming a capacitor structure for a memory element of an integrated circuit. The method comprises providing a first conductive electrode, forming a layer of a first dielectric material thereon, opening a via hole through the dielectric layer, providing within the via opening a capacitor dielectric having a higher dielectric strength than the first dielectric, the capacitor dielectric contacting the first electrode, planarizing the resulting structure and then forming a second conductive electrode thereon. Preferably, when the second dielectric comprises a ferroelectric dielectric material, sidewalls of the via opening are lined with a dielectric barrier layer to provide diffusion barrier between the ferroelectric and first dielectric layer. Advantageously, planarization is accomplished by chemical mechanical polishing to provide fully planar topography. The method provides a capacitor of a simple, compact structure which may be integrated with CMOS, Bipolar and Bipolar CMOS processes for submicron VLSI and ULSI integrated circuits.
Calder Iain D.
Emesh Ismail T.
Ho Vu Q.
Jolly Gurvinder
Madsen Lynnette D.
Calder Iain D.
de Wilton Angela C.
Emesh Ismail T.
Ho Vu Q.
Jolly Gurvinder
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